What will computer chips look like in 2045?
Summary
Dwarkesh Patel interviews Intel executives to dissect the semiconductor industry's AI-driven demand surge and the complexities of manufacturing advanced chips. The discussion covers the transition to Gate All Around transistors, the strategic adoption of high-NA EUV lithography, and lessons learned from past process delays. The episode also explores future technologies like CFETs and ruthenium interconnects, highlighting the balance between innovation and schedule reliability in Intel's foundry strategy.
Topics discussed
AI demand shock and capacity constraints
Process development, yield, and defect analysis
Lessons from the 10nm delay and EUV readiness
Transistor evolution from planar to FinFET
Gate All Around challenges and R&D iteration
The golden age of innovation and new materials
High NA lithography and backside power benefits
Transitioning to foundry model and PDK maturity
Sponsor segment: WorkOS enterprise features
Future transistor structures and 3D stacking
CFET thermal and power efficiency challenges
Hot Topics meetings and production risk decisions
Epitaxy defects and processor trace debugging
Sponsor segment: Jane Street and Magic Trace
Parallel problem solving and hotbox prioritization
Ruthenium interconnects and material maturity
Research lab: CFET, 2D materials, and test vehicles
Advanced packaging evolution and hybrid bonding
Sponsor segment: Antithesis deterministic testing
Die-to-wafer bonding and non-AI applications
Supply chain bottlenecks and capacity limits
Economies of scale and industry consolidation
Intel vs TSMC: Catching up on scale and tech
Future production forecasts and vertical integration
Capital intensity, risk aversion, and investment
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